The present invention relates to voltage supply stabilization and, in particular, to a decoupling capacitor arrangement for integrated circuit devices that incorporate the decoupling capacitor arrangement, and to methods of manufacturing the foregoing.
An integrated circuit (IC) is often incorporated in electronic subassemblies by mounting the same to a printed circuit board (PCB) to facilitate input-output I/O connections thereto. To that end, PCBs have electrically conductive traces electrically connected to I/O pads of the IC. I/O signals that propagate along the I/O connections include address, control or data signals, power and ground. Characterized by high frequency operational speeds, ICs operate so as to minimize signal noise.
One manner by which to minimize signal noise is to minimize bias voltage fluctuations, which may result from, inter alia, varying loads on a power supply employed to bias the IC. Varying loads may result from operational characteristics of the IC, such as switching circuitry. This may result in a lower operational frequency of the IC compared to the operational frequency of the same IC in the presence of a voltage supply having less or no fluctuations in the voltage provided to the IC.
One manner in which to stabilize the voltage level provided to an IC by a power supply is to use a decoupling capacitor. As is well known, a decoupling capacitor is connected between a supply voltage line and the reference for the supply voltage line, typically ground. The connection is typically located proximate to the switching load, which in the present discussion is the IC. The result is that the capacitor periodically charges and discharges so that the IC draws full current at normal voltage from the power supply to attenuate the reduction in voltage supplied during operation. Drawbacks of decoupling capacitors are that the foot print of the same limits the layout configuration on the PCB and slows manufacturing throughput. In addition, the operational benefits of decoupling capacitors are reduced due to the foot print of the same, because it is difficult to minimize the distance between the decoupling connection and the IC.
A need exists, therefore, to provide improved decoupling techniques for integrated circuits.